Totem

Totem is a full-chip noise integrity platform for analog and mixed-signal designs. It addresses the challenges associated with global couplings of power/ground noise, substrate noise, and package/PCB capacitive and inductive noise for analog, mixed-signal, memory, and high-speed I/O designs. Totem considers the impact of full-chip SoC substrate noise (SE) by directly interfacing with RedHawk to obtain accurate substrate injection signature for all digital components. Totem accurately analyzes noise coupling effects at every time-point using a single kernel solver, enabling designers to account for all global noise impact on their design.

Integrated with existing analog design environment, Totem is a full-chip layout driven analysis solution providing cross-probing of analysis results with industry standard circuit design tools. Designers can use Totem for early-stage prototyping to guide their power network and package design, as well as for accurate chip sign-off.

	A transistor-level P/G noise analysis and verification solution for static and dynamic power integrity from early stage in the design to sign-off.
	The only commercially available solution for modeling and simulating substrate-based noise coupling at the full-chip level.
	A proven device-level, RLC parasitic extraction for custom designs.
	The industry's first comprehensive electro-static discharge (ESD) integrity solution.