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- SentinelChip-Package-System Convergence: Power/Signal Integrity, IO-SSO, Thermal, and EMI
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- RTL to SiliconRTL power reduction, analysis, and signoff
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RTL to Silicon
RTL to Silicon
Solutions for Ultra Low Power Initiatives
Power is a driving force in today’s designs and to address the low power requirements, the design teams need to adopt a power-aware design methodology that considers power from early in the design phase and throughout the entire design process. By addressing power at the RTL design phase, designers can ensure that power is a key consideration in their design process, and reductions otherwise not possible without significant changes in a synthesized netlist are achieved early on.
Power reduction techniques like clock gating, voltage islands, and power gating can affect the power integrity of the design’s power delivery network. Extensive simulations need to be done all the way to tape-out to prevent failures. These simulations should be started from very early in the design process considering the realistic power numbers and worst case switching scenarios based on RTL power analysis. This can help in power grid and decap planning, package selection, and other design decisions.
Power, Noise and Reliability Requirements for RTL to Silicon Flow
Apache’s Power, Noise, and Reliability platforms provide a unique RTL to Silicon flow with the following technologies:
- Power estimation and reduction during the RTL design phase
- Early power delivery network prototyping and package planning using RTL simulation data
- RTL vector driven and VectorLess based power grid validation (noise, reliability) through the design process to sign-off
The following figure captures the RTL to Silicon flow using Apache technologies:
RTL Power Analysis
PowerArtist™, the industry’s leading RTL power management solution enables RTL designer to understand the where, the when, and the how of power and activity. PowerArtist provides comprehensive simulation vector analysis, RTL power analysis, and automatic RTL power reduction for a complete RTL Design-for-Power (DFP™) solution. It leverages built-in RTL power estimation and analysis engine for accurate analysis-driven optimization at all stages of the design. Power bugs can be easily identified with its powerful but intuitive graphical environment and a user-programmable interface.
PowerArtist provides the following technologies:
- Micro-architectural level power prediction and exploration
- Incremental refinement of RTL through block-level and full-chip analysis and optimization
- Design partitioning for power gating and voltage islands
- Full-chip RTL power analysis
- RTL vector selection, gate-level power consumption verification, and sign-off
RTL Interface Data Generation for Early PDN Analysis
Once RTL power analysis is done, power bugs identified, and design optimized, PowerArtist can generate RTL interface models for each block in the design by capturing relevant electrical data (average power, switching current, device RC parasitics) that can then be used for several purposes such as early power grid prototyping, early Chip Power Model (CPM™) creation, and package selection and planning.
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The RTL interface models generated by PowerArtist can be used for accurate early static and dynamic voltage drop analysis. By using the worst case switching scenario information from an RTL simulation, RedHawk accurately predicts high voltage drop scenarios even without having physical design available, thus allowing the designers to modify their PDN design to avoid encountering failures late in the design process.
Power Sign-off
The RedHawk™ power integrity analysis platform enables designers to validate and sign-off the power grid of their designs from noise and reliability considerations. The use of power reduction technologies like power and clock gating can adversely impact the power grid noise in the circuit. For example, turning on and off the clock tree network introduces significant change in the current signature of a design which along with the package inductance can cause high Ldi/dt induced voltage drop. By using proprietary extraction and simulation technologies, RedHawk can simulate even the largest of designs at pico-second time-domain resolution either using test-vectors from RTL simulations or its VectorLess engine. In addition, its Explorer interface allows designers to identify the root-cause of dynamic voltage drop issues and provides an environment for exploring fixes that can be verified through incremental analyses before committing those to layout.
RTL to Silicon Flow
As designers look to reduce their operational and/or standby power, they need to start early by establishing power as a design target during their micro-architecture and RTL design process. By leveraging the analysis driven reduction techniques available in PowerArtist-XP, they can explore different power saving modes not restricting themselves to one approach only. Once the RTL optimizations are done and synthesized netlist is available, layout based power integrity analyses must be performed to quantify the success of the RTL stage optimizations and to ensure that the voltage drop in the chip is contained. These simulations must be done in the context of the system in which the final fabricated chip will reside (e.g. package and PCB). The successful design and delivery of a low power chip requires a comprehensive Design-for-Power methodology that spans its entire design process.