- Products
- PowerArtistRTL Design-for-Power: Power Reduction, Analysis, and Debug
- RedHawkSoC Power Integrity: Dynamic Power, Advanced Low Power, Reliability, and Chip-Package Co-design
- TotemAnalog Power, Noise and Reliability: Dynamic Power, Substrate Noise, EM, and ESD
- SentinelChip-Package-System Convergence: Power/Signal Integrity, IO-SSO, Thermal, and EMI
- Flows
- RTL to SiliconRTL power reduction, analysis, and signoff
- Analog to DigitalFull-chip mixed-signal power, noise, and reliability
- Chip-Package-SystemChip, package, system co-design / co-analysis
- Support
- Community
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- About ApacheOverview, Management Team, Achievements
- News
- Events
- Employment
- Global Offices
Blog
Blog
Meet Apache’s Blog authors and read their informative technical posting on topics covering low power, analog design, IC/Package/SIP, and more.
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Aveek is Vice President of Product Engineering and Support. Since joining in 2003 as a senior applications engineer, Aveek has taken on various roles and responsibilities at Apache including a Director of Product Engineering. | Posts |
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Bhavana is Manager of Strategic Initiatives working on power and noise analysis initiatives with a key focus on die, system, and cross-domain analysis and optimization. Her areas of expertise include power noise issues such as IR-drop, EM, ESD, EMI, jitter, SSO, etc. and chip-system convergence. | Posts |
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Jerome is Principal Product Engineer providing technical support to the European customers and driving the direction for Apache's power and noise products. Prior experience focused on different implementation tools such as Place & Route and Power Analysis and also include analog/digital full-custom circuit design and analog integration. | Posts |
